Eliyan: The Ultimate Chiplet Interconnect
Backed by Every Major HBM and Foundry, Built by Networking Pioneers
It’s been a while since we checked in on semiconductor startups, but they remain one of the best ways to glimpse the industry’s future. What problems are they solving, and what clever approaches are they taking?
With connectivity stocks running hot ( ALAB 0.00%↑ ANET 0.00%↑ AVGO 0.00%↑ CRDO 0.00%↑ CSCO 0.00%↑ MRVL 0.00%↑ etc ), it’s a good time to spotlight Eliyan.
And here’s a fun segue to introduce Eliyan’s CEO Ramin Farjadrad.
Ramin Farjadrad’s Story
Just yesterday, Infineon announced it completed the acquisition of Marvell's Automotive Ethernet business for $2.5B. This particular line of business has roots back in Marvell’s 2019 acquisition of Aquantia for $450M. That’s a nice 5x flip btw!
Aquantia pioneered multi-gigabit Ethernet solutions that became IEEE standards and helped drive the company to a successful IPO before the acquisition. And Aquantia was co-founded by none other than Eliyan co-founder Ramin Farjadrad.
Here’s a fun video of Ramin at Aquantia talking about lessons learned as a serial technology entrepreneur from back in 2016:
Ramin earned his Ph.D. in Electrical Engineering from Stanford, where he developed one of the first gigabit transceivers built entirely in CMOS. At the time, such high-speed links were almost exclusively made in exotic processes like GaAs. Farjadrad pushed performance from 1 Gbps to 10 Gbps, proving that mainstream CMOS could deliver multi-gigabit signaling without the cost or complexity of mixed-process designs.
Check out his May 2000 paper A 0.3-um CMOS 8-Gb/s 4-PAM Serial Link Transceiver:
After Stanford, Ramin founded Velio Communications to commercialize multi-gigabit SerDes for terabit-class optical switches, aiming to solve long-haul and WAN interconnect bottlenecks during the early internet buildout. The company secured substantial pre-orders of roughly $500 million from Nortel and Lucent, but the 2001 optical market crash caused demand to collapse almost overnight, ultimately forcing a sale of some assets to Rambus and the rest of the compay to LSI. In the YouTube video above, Ramin mentions how the experience underscored the risks of overconcentration in a single vertical and the importance of maintaining roadmap diversification.
Ramin went on to found Aquantia with the goal of leapfrogging the industry in 10 Gbps Ethernet over twisted-pair copper (10GBASE-T) at a fraction of the cost of optical modules. The company solved the technical barrier by reducing per-port PHY power from roughly 15 watts to under 5 watts, enabling deployment in high-density switches and servers. Importantly, they focused on commodity-friendly infrastructure, using standard connectors and unshielded Cat-5/6 cabling to allow simple, low-cost installation without the complexity of fiber handling. This approach secured Cisco design wins and established Aquantia as the leader in low-power 10GBASE-T solutions.
Farjadrad and Aquantia also helped shape Ethernet standards through its work in the NBASE-T Alliance and the IEEE 802.3bz task force, which sped adoption in enterprise networks, especially for high-speed Wi-Fi backhaul. (Source, Anandtech RIP). Industry standards… talk about street cred.
Now, this serial entrepreneur is building yet another communications company, Eliyan.
Ramin and his Eliyan co-founders Syrus Ziai and Patrick Soheili have raised >$100M from investors including Samsung, SK Hynix, Micron, Intel Capital, Tiger Global, TSMC’s venture arm, and others.
It’s interesting to note that all three big HBM suppliers are investors… and all three major foundries too!
Other notable backers include Tracker Capital, founded by Stephen Feinberg, now the U.S. Deputy Secretary of Defense, and Celesta Capital, co-founded by current Intel CEO Lip-Bu Tan.
With that context, let’s look at Eliyan itself and the problem it’s out to solve.
Eliyan
Connecting dies inside a package is incredibly important for datacenter AI and will only become more so as we enter the chiplet era. One of the most performance-sensitive examples is HBM to GPU; the HBM logic die must move massive amounts of data to the AI accelerator with minimal latency and energy consumption.
Today, the industry relies on silicon interposers to carry the connections between die.
But interposers have tradeoffs.
The Interposer Problem
The industry has long favored silicon interposers over organic package substrates for carrying connection between die because interposers are manufactured with semiconductor lithography rather than PCB-style processes, allowing much finer bump pitch and line spacing. This precision enables far more interconnects per millimeter of die edge, directly increasing bandwidth density between dies. Silicon’s uniform, low-loss electrical characteristics support higher per-lane data rates at lower power and allow extremely short, direct die-to-die connections with minimal latency. These attributes are critical in high-performance systems such as datacenter CPUs, GPUs, and HBM memory stacks, where organic substrates cannot meet the necessary signal integrity or performance requirements.
SemiAnalysis has a nice recent article about it, highly recommend: Scaling the Memory Wall: The Rise and Roadmap of HBM
But most industry watchers know that interposers are a supply chain bottleneck. TSMC’s CoWoS capacity has been constrained for years, which keeps Nvidia’s GPUs in short supply. Demand for CoWos is high across the board from anyone building an AI accelerator, whether GPU or XPU.
TSMC and others are scrambling to expand their manufacturing capacity to keep up.
Of course, there’s a near monopoly on interposer supply today too. Intel Foundry has interposer technology (EMIB), and so do OSATs like Amkor, but TSMC with their CoWoS variants has the majority of customers. It goes without saying there are geopolitical considerations with concentrated, limited supply.
Yet Interposer supply is a near-term constraint. But there are more fundamental trade-offs.
Large silicon interposers can cost orders of magnitude more than traditional PCB packaging due to their complexity and extra process steps. That price confines interposers (and high-performance chiplets) only to applications that can absorb the cost…. which is pretty much just datacenter SoCs.
They also bring thermal and mechanical challenges. Fine-pitch microbumps are mechanically fragile, limiting their use in rugged environments like automotive and defense. And placing HBM directly beside compute dies for maximum bandwidth creates thermal coupling between hot logic die and heat-sensitive memory, reducing layout flexibility and increasing system-level reliability risk.
But don’t take my word for it. Here’s a report from Meta recounting the failures during their 54-day Llama 3 training run. 17% of failures from HBM!
Finally, most interposer packaging flows are proprietary to a single foundry or OSAT, reinforcing both supply chain and geopolitical risk we discussed earlier.
Even so, for AI accelerators, the performance gains have so far outweighed those trade-offs.
From SemiAnalysis,
The implication of having much more I/O is increased routing density and complexity. Each I/O requires an individual wire/trace, with additional wiring required for power and control. For a HBM3E stack, there are over a 1,000 wires between the adjacent XPU and the HBM. This level of routing density is not achievable on a PCB or package substrate; therefore, an interposer (silicon or organic) in a 2.5D package assembly like CoWoS is required.
Silicon interposers are expensive, but for now, they’re indispensable. “An interposer… is required.”
Yes, chiplet interconnect standards like UCIe can be implemented on organic substrates, but at the cost of lower performance than a silicon interposer.
That raises a question: what if an application can’t absorb the cost, thermal load, or mechanical fragility of a silicon interposer? Imagine faster, higher-capacity memory in smartphones to run local AI…
What if silicon interposer performance were possible on a cheaper, more robust organic substrate?
Eliyan says it is. Its NuLink PHY lets designers reach performance levels on organic substrates that other PHYs achieve only with silicon interposers
How NuLink Works
In a typical setup, the NuLink chiplet sits alongside other dies in a multi-die package, while the main ASIC—whether a GPU, AI accelerator, or custom compute chiplet—integrates Eliyan’s PHY IP to communicate directly with NuLink.
This separation moves the highest-performance die-to-die interconnect off the main logic chip, giving designers the bandwidth and latency advantages of advanced signaling without the burden of building and validating complex analog PHY circuits themselves.
NuLink is protocol-agnostic, supporting standard chiplet interconnects like UCIe and BoW as well as proprietary high-performance links.
Benefits: Supply Chain, Cost, and Time to Market
NuLink’s most disruptive advantage is enabling silicon-interposer-class performance on inexpensive, robust organic substrates. The shift carries several strategic consequences.
First, it breaks the near-monopoly on high-bandwidth die-to-die links held by advanced packaging flows like TSMC’s CoWoS. Organic substrates are made in larger can be sourced from a broader range of vendors worldwide. This diversification mitigates geopolitical risk.
Second, organic substrates are mechanically tougher than fine-pitch silicon interposers. They can survive the shock and vibration demands of automotive, aerospace, and industrial systems—markets largely shut out from HBM-class performance due to interposer fragility. NuLink makes those markets accessible to chiplet-based designs.
Third, organic substrates larger maximum size gives designers more real estate for chiplets. That space can be used to add compute dies or scale memory capacity beyond current interposer-based system limits.
High-Performance Mode on Silicon Interposers
NuLink is not just an “organic substrate enabler” though. Even in the high-end designs that will still use silicon interposers or embedded bridges, NuLink delivers a step-function in performance.
In a given process node, it can double the per-lane bitrate at lower power compared to other PHYs. That translates into higher absolute bandwidth between dies, more bandwidth per millimeter of die edge (“beachfront”), and a smaller fraction of the system power budget spent just on moving bits.
In bandwidth-bound workloads like LLM inference, those gains directly expand the performance ceiling.
So NuLink PHY can be both a cost/supply-chain hedge or a performance enabler.
Eliyan’s NuLink lets architects choose the substrate and packaging technology that best fits their product roadmap, without sacrificing interconnect performance.
For organic substrates, it enables interposer-class bandwidth density; for silicon interposers, it stretches the physical limits of beachfront utilization.
And in both cases, its simultaneous bidirectional signaling (SBD) doubles effective throughput for a given edge length.
Subscribers: NuLink & the Memory Wall + Eliyan’s Go-to-Market Opportunities
The core challenge for any die-to-die interconnect is the memory wall. As we’ve been discussing, Eliyan has a way to bridge that. We’ll dig even deeper for subscribers. For example, where does HBM4/e come into play?
From there, we’ll explore Eliyan’s go-to-market opportunities:
Who are the most likely early adopters?
Which partners could amplify its reach?
How could Eliyan evolve from a point-solution provider into an embedded part of the AI hardware infrastructure?