ARM’s Chiplet System Architecture Streamlines Chip Design
Bill: Everybody’s interested in chiplets these days, but trying to get them to actually work together can be a challenge. Arm has been doing some really groundbreaking stuff. Can you tell us about your latest announcement?
Eddie: Yeah. Well, Bill, we’re happy to be here at the Chiplet Summit talking about the public release of Arm’s new Chiplet System Architecture (CSA) specification. We really think it’s important to work through a standards-based approach to be able to get chiplets that can actually be interoperable. Composing silicon from reusable chiplets can only really happen if people are building towards a common standard to achieve this sort of interoperation. We have released our first public spec, just in time for the first day of the Chiplet Summit. We’ve had over 60 partners working with us to get the specification up to this point, and we’re always looking for more partners to collaborate with us.
Bill: Can you talk a little bit more about the underlying standards that are employed, or is it using things like UCIe, AMBA? How does that all fit together?
Eddie: That’s a good question. We’re a big proponent of standard physical interfaces, and Arm has been on the board of UCIe to help promote it as a viable standardized interface between chiplets. The CSA focuses on system-level design above the physical layer—what protocols should run between chiplets. We’re a strong supporter of the AMBA protocol, used in many Arm systems today, and we’ve developed a revision of AMBA CHI that runs over chiplets. The spec also addresses logical partitioning—for example, designing systems with compute on one die and I/O on another. It provides framework and terminology for system designers so they can issue RFIs aligned to CSA, making vendor collaboration easier.
Bill: So how does this fit with a lot of the Arm IP you have out there? Is this something that makes it easier for designers to incorporate that?
Eddie: It will. We want to get to a point where chiplet products are CSA-compliant, and Arm IP will be designed to enable that compliance. We’re actively working on compute subsystems for compute chiplets and expanding our IP interconnect to connect not just multicore Arm SoCs, but also accelerator chiplets. Our vision is chiplets with coherent memory access and shared memory domains, enabling more powerful system composition.
Bill: I know it’s just the starting point at this point, but where do you see this going in the future? Will there be an additional organization around this to provide compliance and things of that nature?
Eddie: A couple of things. We’ll evolve the spec to address multi-chiplet boot, security, and telemetry across multiple chips. We’re also working with partners on developing compliance programs and test suites so vendors can validate CSA compliance.
Bill: Excellent. Sounds like an exciting future.
Eddie: We want chiplets to be as easy to use as PCIe cards are today. Bringing that system-level standardization down to the package level requires the same kind of standards and compliance infrastructure.
Bill: Thank you very much.
Eddie: Thank you.